EP910JC-30 vs EP910PI-20 对比
详细并排对比 EP910JC-30 出自 Intel 和 EP910PI-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910JC-30 | EP910PI-20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $9.75 |
| Family | Classic EPLD (MAX-style) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM (UV-erasable windowed variants available) |
| 封装 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PDIP-40 (PI suffix) |
| 工作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| 安装类型 | Surface Mount (socket-mountable) | Through-Hole |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | unknown |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Device Family | — | Altera Classic EPLD Family |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |