EP910JC-30 vs EP910PI-20 Vergleich

Detaillierter Direktvergleich von EP910JC-30 von Intel und EP910PI-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910JC-30 EP910PI-20
Marke Intel Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $9,75
Family Classic EPLD (MAX-style) —
Propagation Delay (tpd) 30 ns —
Maximum Internal Frequency (Fmax) 33.3 MHz —
Macrocells 24 24
Inputs 36 —
Product Terms 240 —
Outputs 10 dedicated —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM, UV-erasable CMOS EPROM (UV-erasable windowed variants available)
Gehäuse 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) PDIP-40 (PI suffix)
Betriebstemperatur [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Supply Current (Icc) [DATA_NEEDED: Icc typical / maximum] —
Montageart Surface Mount (socket-mountable) Through-Hole
RoHS-Status [DATA_NEEDED: RoHS compliance] unknown
Logic Blocks 24 macrocells (AND/OR array architecture) —
Device Family — Altera Classic EPLD Family
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5 V (+/- 5%)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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