EP910LC-40H vs EP910DC-40 对比
详细并排对比 EP910LC-40H 出自 Altera 和 EP910DC-40 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910LC-40H | EP910DC-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $13.95 |
| Family | Classic EPLD (EP910) | — |
| Macro Cells | 24 | — |
| Usable Gates | 450 | — |
| Logic Elements | 24 macro cells / expandable to 48 via expander terms | — |
| Propagation Delay (tPD) | 40 ns max | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | Low-power CMOS, typical ICC < 100 mA | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封装 | 40-pin Ceramic DIP (CDIP-40), JEDEC standard | DIP-40 (ceramic, through-hole) |
| 安装类型 | Through-Hole (THT) | Through-Hole |
| 工作温度 | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] | — |
| Speed Grade | -40 (40 ns tPD) | — |
| Programming Method | UV-erase + EPROM program, ~100 erase cycles | UV-erase + EPROM programmer; on-board logic test circuitry |
| I/O Pins | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] | — |
| RoHS 状态 | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] | [DATA_NEEDED: rohs_status] |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 电源电压 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |