EP910PC-15 vs EP610PC-15 对比

详细并排对比 EP910PC-15 出自 Altera 和 EP610PC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910PC-15 EP610PC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $12.80 $17.50
Family Altera Classic EPLD Classic EPLD
Usable Gates 900 300 gates
Macrocells 24 16
Maximum Pin-to-Pin Delay (tpd) 15 ns —
Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
Supply Current (Icc) 80 mA typical —
Dedicated Inputs 10 —
Dedicated I/O Pins 12 —
工作温度 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
封装 24-pin PDIP (PDIP-24, 0.300 inch) PDIP-24 (plastic DIP, 24-pin)
安装类型 Through-Hole Through-Hole (DIP)
Process Technology CMOS, UV-erasable —
Programming Method Altera Logic Programmer card —
RoHS 状态 [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] [DATA_NEEDED: RoHS status]
MSL 等级 Not applicable (through-hole) —
Device Type — EPLD (Erasable Programmable Logic Device)
Logic Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency — 100 MHz (per family datasheet)
Pipelined Data Rate — Up to 100 MHz
Technology — CMOS
Architecture — PAL-type, sum-of-products AND/OR array
TTL Emulation — 100% TTL compatible
引脚数量 — 24 pins
Development Tool — Altera MAX+PLUS II
Logic Test Circuitry — On-board for AC/DC verification

数据手册与资源

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