EP910PC-35 vs EP910PC30T 对比

详细并排对比 EP910PC-35 出自 Altera 和 EP910PC30T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910PC-35 EP910PC30T
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.70 $8.85
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 24 —
I/O Pins 24 —
Dedicated Inputs 12 —
Total Inputs 36 —
Product Terms 240 —
Propagation Delay (tPD) 35 ns 30 ns
Maximum Counter Frequency 37 MHz —
Internal Performance Frequency 100 MHz —
Technology CMOS, UV-erasable/OTP —
电源电压 5 V —
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
封装 40-pin PDIP (Plastic DIP) 24-pin PDIP (PC)
安装类型 Through-Hole Through-Hole (THT)
Architecture PAL-type sum-of-products, AND/OR array —
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools —
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] —
Device Series — EP910
Number of Macrocells — 24
Number of I/O Pins — 24
Number of Dedicated Inputs — 12
Maximum Product Terms — 240
Maximum Clock Frequency (fMAX) — 33.3 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Process Technology — CMOS
Programmable Logic Architecture — PAL-type sum-of-products, EPLD
Speed Grade — -30 (30 ns tPD)
Programming Technology — EPROM (OTP in plastic package, UV-erasable in windowed package)
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]
引脚数量 — 24

数据手册与资源

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