EP910PC-35 vs EP910PC30T Comparison
Detailed side-by-side comparison of EP910PC-35 by Altera and EP910PC30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PC-35 | EP910PC30T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | — |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | 30 ns |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | — |
| Supply Voltage | 5 V | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Package | 40-pin PDIP (Plastic DIP) | 24-pin PDIP (PC) |
| Mounting Type | Through-Hole | Through-Hole (THT) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | — |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| Programming Technology | — | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance status] |
| Pin Count | — | 24 |