EP910PC-35 vs EP910PC30T Comparison

Detailed side-by-side comparison of EP910PC-35 by Altera and EP910PC30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP910PC-35

EP910PC-35 - 35ns 24-Macrocell EPLD | Altera | Classic EPLD

EP910PC-35 Obsolete

Specification Comparison

Parameter EP910PC-35 EP910PC30T
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.70 $8.85
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) β€”
Macrocells 24 β€”
I/O Pins 24 β€”
Dedicated Inputs 12 β€”
Total Inputs 36 β€”
Product Terms 240 β€”
Propagation Delay (tPD) 35 ns 30 ns
Maximum Counter Frequency 37 MHz β€”
Internal Performance Frequency 100 MHz β€”
Technology CMOS, UV-erasable/OTP β€”
Supply Voltage 5 V β€”
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Package 40-pin PDIP (Plastic DIP) 24-pin PDIP (PC)
Mounting Type Through-Hole Through-Hole (THT)
Architecture PAL-type sum-of-products, AND/OR array β€”
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools β€”
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] β€”
Device Series β€” EP910
Number of Macrocells β€” 24
Number of I/O Pins β€” 24
Number of Dedicated Inputs β€” 12
Maximum Product Terms β€” 240
Maximum Clock Frequency (fMAX) β€” 33.3 MHz
Supply Voltage (VCC) β€” 5 V (4.75 V to 5.25 V)
Process Technology β€” CMOS
Programmable Logic Architecture β€” PAL-type sum-of-products, EPLD
Speed Grade β€” -30 (30 ns tPD)
Programming Technology β€” EPROM (OTP in plastic package, UV-erasable in windowed package)
RoHS Status β€” [DATA_NEEDED: RoHS compliance status]
Pin Count β€” 24

Datasheets & Resources

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