EP910PC-35 vs EP910PC30T Vergleich

Detaillierter Direktvergleich von EP910PC-35 von Altera und EP910PC30T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PC-35 EP910PC30T
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,70 $8,85
Family Classic EPLD Altera Classic EPLD
Device Type EPLD (Erasable Programmable Logic Device) —
Macrocells 24 —
I/O Pins 24 —
Dedicated Inputs 12 —
Total Inputs 36 —
Product Terms 240 —
Propagation Delay (tPD) 35 ns 30 ns
Maximum Counter Frequency 37 MHz —
Internal Performance Frequency 100 MHz —
Technology CMOS, UV-erasable/OTP —
Versorgungsspannung 5 V —
Betriebstemperatur [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Gehäuse 40-pin PDIP (Plastic DIP) 24-pin PDIP (PC)
Montageart Through-Hole Through-Hole (THT)
Architecture PAL-type sum-of-products, AND/OR array —
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools —
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] —
Device Series — EP910
Number of Macrocells — 24
Number of I/O Pins — 24
Number of Dedicated Inputs — 12
Maximum Product Terms — 240
Maximum Clock Frequency (fMAX) — 33.3 MHz
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Process Technology — CMOS
Programmable Logic Architecture — PAL-type sum-of-products, EPLD
Speed Grade — -30 (30 ns tPD)
Programming Technology — EPROM (OTP in plastic package, UV-erasable in windowed package)
RoHS-Status — [DATA_NEEDED: RoHS compliance status]
Pin-Anzahl — 24

Datenblätter & Ressourcen

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