EP910PI-20T vs EP910PI-20 对比

详细并排对比 EP910PI-20T 出自 Intel 和 EP910PI-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP910PI-20T EP910PI-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $9.95 $9.75
Family Altera Classic EPLD —
Device EP910 —
Number of Macrocells 24 —
Number of Usable Gates [DATA_NEEDED: usable gate count] —
Propagation Delay (tpd) 20 ns —
Maximum Toggle Frequency 62.5 MHz —
Number of Dedicated Inputs 12 —
Number of I/O Pins 20 —
引脚数 40 —
封装 PDIP-40 (PI) PDIP-40 (PI suffix)
安装类型 Through-Hole (DIP) Through-Hole
Technology CMOS EPROM (UV-erasable) CMOS EPROM (UV-erasable windowed variants available)
工作温度 [DATA_NEEDED: operating temperature range] -40C to +85C (industrial)
Programming Standard EPROM programmer, JEDEC map —
RoHS 状态 unknown unknown
生命周期状态 Not Recommended for New Designs (NRND) —
Device Family — Altera Classic EPLD Family
Macrocells — 24
Propagation Delay (tPD) — 20 ns
Supply Voltage (VCC) — 5 V (+/- 5%)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

数据手册与资源

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