EP910PI-20T vs EP910PI-20 Comparison
Detailed side-by-side comparison of EP910PI-20T by Intel and EP910PI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-20T | EP910PI-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Number of Pins | 40 | — |
| Package | PDIP-40 (PI) | PDIP-40 (PI suffix) |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM (UV-erasable windowed variants available) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Programming | Standard EPROM programmer, JEDEC map | — |
| RoHS Status | unknown | unknown |
| Lifecycle Status | Not Recommended for New Designs (NRND) | — |
| Device Family | — | Altera Classic EPLD Family |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V (+/- 5%) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |