EPC16QC100T vs EPC16QC-100T 对比

详细并排对比 EPC16QC100T 出自 Altera 和 EPC16QC-100T 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC100T EPC16QC-100T
品牌 Altera Altera
分类 Memory ICs Memory ICs
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $17.95 $14.50
存储器类型 In-System Programmable Configuration PROM Flash Configuration PROM (in-system programmable)
存储容量 16 Mbit —
接口 Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V —
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) —
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
封装 PQFP-100 (20 x 14 mm) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (commercial) [DATA_NEEDED: Operating temperature range]
Lead-Free / RoHS Depends on date code; verify per lot —
MSL 等级 3 (per JEDEC J-STD-020) [DATA_NEEDED: Moisture sensitivity level]
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] —
Memory Density — 16 Mbit (2 Mbyte)
Supported FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
电源电压 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
RoHS 状态 — unknown
Lead-Free — unknown

数据手册与资源

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