EPC16QC100T vs EPC16QC-100T 비교

다음의 상세 나란히 비교: EPC16QC100T 제조: Altera 및 EPC16QC-100T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPC16QC100T EPC16QC-100T
브랜드 Altera Altera
카테고리 Memory ICs Memory ICs
수명 주기 상태 NRND Obsolete
재고 상태 In Stock In Stock
단가 (USD) $17.95 $14.50
메모리 유형 In-System Programmable Configuration PROM Flash Configuration PROM (in-system programmable)
메모리 크기 16 Mbit —
인터페이스 Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V —
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) —
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
패키지 PQFP-100 (20 x 14 mm) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
실장 유형 Surface Mount Surface Mount
동작 온도 0C to +70C (commercial) [DATA_NEEDED: Operating temperature range]
Lead-Free / RoHS Depends on date code; verify per lot —
MSL 레벨 3 (per JEDEC J-STD-020) [DATA_NEEDED: Moisture sensitivity level]
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] —
Memory Density — 16 Mbit (2 Mbyte)
Supported FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
공급 전압 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
RoHS 상태 — unknown
Lead-Free — unknown

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