EPC2L120N vs EPC2L120 对比
详细并排对比 EPC2L120N 出自 Intel 和 EPC2L120 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2L120N | EPC2L120 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | Memory ICs |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.85 | $5.20 |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | EPC2 (Enhanced Configuration) |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| 封装 | 84-pin PLCC (J-Lead) | PLCC-20 |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| 工作温度 | [DATA_NEEDED: industrial temp range] | -40 C to +85 C |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | — |
| RoHS 状态 | unknown | unknown |
| 存储器类型 | — | Configuration PROM (Flash-based) |
| Density | — | 120 Kbit |
| Configuration Interface | — | Serial, FPGA-targeted |
| Operating Voltage | — | 2.7 V to 3.6 V (3.3 V typ) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Compatible FPGAs | — | Altera Cyclone, Cyclone II, APEX-series |
| CONF_DONE Output | — | Open-drain, wire-OR capable |
| Data Retention | — | 20 years (per Altera datasheet family) |
| Program/Erase Cycles | — | 100 cycles minimum |
| 安装类型 | — | Surface Mount |
| Lead-Free | — | unknown |