EPC2L120 - 2.7V-3.6V 120Kbit Config Device | Altera | PLCC-20
料号： EPC2L120 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $7.95 | $79.50 |
| 100 | $6.85 | $685.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.2 | $5,200.00 |
EPC2L120 概述
Key specifications include an operating voltage range of 2.7V to 3.6V (3.3V typical), a storage capacity of 120 Kbit, in-system programmability via IEEE 1149.1 (JTAG) boundary-scan, and a serial configuration interface that streams configuration data to the target FPGA. The device operates across the industrial -40C to +85C temperature range and supports multiple package options including PLCC-20 and SOIC-20 footprints for drop-in PCB layout reuse.
The EPC2L120 utilizes an internal flash memory array combined with a dedicated serial configuration controller. Unlike older EPC1 devices, the EPC2 family adds 3.3V operation, in-system programmability (ISP), and an open-drain CONF_DONE output that can be wire-ORed with the FPGA's CONF_DONE pin. This allows multi-device configuration chains and seamless in-field firmware updates without removing the configuration memory from the board.
Typical applications include Altera Cyclone series FPGA configuration on PCI cards, embedded industrial controllers, telecom line cards, test & measurement instruments, and any low-volume or in-field-reprogrammable design where a parallel flash PROM is over-specified. The 120 Kbit density is well-matched to mid-sized LUT-based FPGAs in the Cyclone/Cyclone II era.
When designing with this device, note that it has been classified as Not Recommended for New Designs (NRND) or end-of-life by Altera/Intel in recent product change notifications - verify the latest lifecycle status with the manufacturer before committing to new designs. Consider the higher-density EPC2LC20 (256 Kbit) or EPC4PC8 for new layouts.
直接替换替代料： EPC2L120 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPC2L120 （相同外形与封装尺寸） ——差异在于 Package, Configuration Interface, Memory Type, Mounting Type, Supported FPGA Families.
快速对比工具——选择替代料号进行并排对比：
EPC2LC20N
✅ 直接替换✓ 有现货
$7.4 / 个
查看数据手册 →EPC2LC20
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPC2C20
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPC2L120 最大额定值与电气特性
| 存储器类型 | Configuration PROM (Flash-based) |
| Density | 120 Kbit |
| Configuration Interface | Serial, FPGA-targeted |
| Operating Voltage | 2.7 V to 3.6 V (3.3 V typ) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| 封装 | PLCC-20 |
| Compatible FPGAs | Altera Cyclone, Cyclone II, APEX-series |
| 工作温度 | -40 C to +85 C |
| CONF_DONE Output | Open-drain, wire-OR capable |
| Data Retention | 20 years (per Altera datasheet family) |
| Program/Erase Cycles | 100 cycles minimum |
| 安装类型 | Surface Mount |
| RoHS 状态 | unknown |
| Lead-Free | unknown |
| Family | EPC2 (Enhanced Configuration) |
EPC2L120 引脚配置
| 引脚 1 | DATA — Serial configuration data output to FPGA |
| 引脚 2 | DCLK — Configuration clock input from FPGA |
| 引脚 3 | nCONFIG — Configuration control input (active low) |
| 引脚 4 | VCC — Power supply (2.7V-3.6V) |
| 引脚 5 | GND — Ground |
| 引脚 6 | TDI — JTAG Test Data In |
| 引脚 7 | TMS — JTAG Test Mode Select |
| 引脚 8 | TCK — JTAG Test Clock |
| 引脚 9 | TDO — JTAG Test Data Out |
| 引脚 10 | NC — Not connected |
| 引脚 11 | NC — Not connected |
| 引脚 12 | CONF_DONE — Configuration done (open-drain, active high) |
| 引脚 13 | nSTATUS — Configuration status (open-drain, active low) |
| 引脚 14 | OE — Output enable (active low) |
| 引脚 15 | nCS — Chip select (active low) |
| 引脚 16 | VPP — Programming voltage supply |
| 引脚 17 | VCC — Power supply (2.7V-3.6V) |
| 引脚 18 | GND — Ground |
| 引脚 19 | NC — Not connected |
| 引脚 20 | NC — Not connected |
典型应用
EPC2L120 适用于 6 应用s: Altera Cyclone FPGA Configuration, Cyclone II FPGA Boot Memory, Industrial Embedded Controllers, Telecom Line Card FPGA Configuration, Test & Measurement Instrumentation, PCI Card FPGA Configuration.
Altera Cyclone FPGA Configuration
The EPC2L120 is purpose-designed to configure Altera Cyclone (EP1C3, EP1C4, EP1C6, EP1C12, EP1C20) SRAM-based LUT FPGAs at power-on. Its 120 Kbit density matches the bitstream size of mid-sized Cyclone devices when using Quartus-generated compressed bitstreams, while its 2.7V-3.6V operating range aligns directly with the Cyclone core VCCINT rail. Engineers place the EPC2L120 between the FPGA's MSEL[2:0] configuration mode pins and the dedicated serial configuration clock/data pins (DCLK, DATA, nCONFIG, CONF_DONE), enabling autonomous FPGA boot without a host processor. Unlike EPC1 generation PROMs, the EPC2L120 supports in-system JTAG reprogramming so firmware updates can be applied in the field without removing the device from the board.
推荐
Cyclone II FPGA Boot Memory
For Altera Cyclone II (EP2C5, EP2C8, EP2C15, EP2C20) designs, the EPC2L120 serves as a compact low-voltage serial configuration memory that interfaces directly to the FPGA's Passive Serial (PS) configuration mode. The EPC2L120's 2.7V-3.6V supply matches the Cyclone II's VCCIO_3 bank that powers the configuration pins, eliminating the need for a separate 5V rail that older EPC1 devices required. In designs where firmware updates are deployed through field service, the EPC2L120's JTAG ISP support allows re-programming via the same JTAG chain used for FPGA debug, dramatically simplifying production programming flow and reducing inventory complexity by stocking a single 3.3V part instead of dual-voltage solutions.
推荐
Industrial Embedded Controllers
The EPC2L120 is well-suited to industrial embedded controller boards built around Altera Cyclone FPGAs, where compact size, low power, and in-field firmware updates are mandatory. Its -40 C to +85 C industrial operating temperature range matches harsh-environment requirements in factory automation, motor control, and process instrumentation. Industrial designs benefit from the EPC2L120's JTAG ISP because field firmware updates can be pushed over Ethernet-to-JTAG bridges (such as Altera USB-Blaster or third-party JTAG-over-TCP servers) without board removal. The PLCC-20 package also supports socketed installation, enabling quick swap during board bring-up, validation, or rework in manufacturing test fixtures.
推荐
Telecom Line Card FPGA Configuration
Telecom line cards frequently use Altera Cyclone or APEX FPGAs for protocol bridging, SERDES glue logic, or TDM switching, and the EPC2L120 serves as a reliable in-system-programmable configuration memory for these designs. Its 120 Kbit density suits mid-sized APEX20K or APEX II bitstreams, while the open-drain CONF_DONE output supports multi-FPGA configuration chains commonly seen on line cards with multiple FPGAs. Telecom designs benefit from the EPC2L120's field-upgrade capability: new protocol stacks or bug fixes can be pushed via JTAG without removing line cards from service, dramatically reducing maintenance costs. The 3.3V-only operation also simplifies power architecture compared to legacy 5V EPC1 designs.
推荐
Test & Measurement Instrumentation
Test and measurement instruments (oscilloscopes, logic analyzers, signal generators, protocol analyzers) commonly deploy Altera Cyclone FPGAs for high-speed data acquisition and DSP, and the EPC2L120 serves as a compact 3.3V configuration memory. Its JTAG ISP support lets test equipment manufacturers ship firmware updates to customers in the field as new protocols or measurement algorithms become available, extending product lifespan without recall. The PLCC-20 socketed option enables easy firmware upgrade during factory calibration, allowing different firmware personalities (e.g., 4G/5G test modes) to be loaded before shipping. The industrial temperature range also suits lab and field test environments.
推荐
PCI Card FPGA Configuration
The EPC2L120 is a natural choice for configuring Altera Cyclone or Cyclone II FPGAs on PCI/PCI-Express add-in cards where board space is constrained and a 3.3V-only power solution simplifies the design. The PLCC-20 package offers a small footprint that fits comfortably alongside high-pin-count BGA FPGAs, and the JTAG ISP interface allows production programming via the PCI card edge connector JTAG test points. Multi-card systems (e.g., DSP accelerator farms, software-defined radio arrays) benefit from the EPC2L120's open-drain CONF_DONE which allows wire-ORed multi-FPGA configuration handshakes for synchronized boot. The 120 Kbit density matches typical Cyclone bitstreams after Quartus compression.
推荐
推荐产品汇总
工程参考数据： EPC2L120 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPC2LC20N | EPC2LC20 | EPC2C20 | EPC2CC20N | EPC1LC20N |
|---|---|---|---|---|---|---|
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Density | 120 Kbit | 256 Kbit | 256 Kbit | 200 Kbit | 200 Kbit | 120 Kbit (5V) |
| Operating Voltage | 2.7V to 3.6V | 2.7V to 3.6V | 2.7V to 3.6V | 2.7V to 3.6V | 2.7V to 3.6V | 4.75V to 5.25V |
| In-System Programmability (JTAG) | Yes | Yes | Yes | Yes | Yes | No (5V legacy) |
| Open-Drain CONF_DONE | Yes | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Lifecycle Status | NRND / EOL track | NRND / EOL track | NRND / EOL track | NRND / EOL track | NRND / EOL track | Obsolete |
| Compatible FPGA Family | Cyclone, Cyclone II, APEX | Cyclone, Cyclone II, APEX (larger bitstreams) | Cyclone, Cyclone II, APEX (larger bitstreams) | Cyclone, Cyclone II | Cyclone, Cyclone II | APEX, FLEX6000/10K (5V legacy) |
关键差异点
- Low-voltage 3.3V operation vs legacy 5V EPC1 family （对比 EPC1LC20N)
- JTAG in-system programmability for field updates （对比 EPC1LC20N)
- 120 Kbit density optimized for mid-sized Cyclone bitstreams （对比 EPC2LC20N)
设计说明
The EPC2L120 must be powered from a clean 2.7V-3.6V rail; ripple above 50 mVpk on the VCC supply can cause configuration read errors during FPGA boot. Place a 0.1 uF ceramic decoupling capacitor as close as possible to pins 4 and 17, with a 10 uF bulk tantalum or ceramic on the same rail. The VPP pin (pin 16) is the programming voltage supply and must be connected to VCC for normal operation; do not leave it floating during in-system programming as this can damage the internal charge pump. Estimated: at 3.3V operation with all outputs static, quiescent current is typically 10-20 mA, peaking during configuration reads at 50 mA per the Altera datasheet family characterization.
Use a 4-layer PCB with a solid ground plane directly beneath the EPC2L120 PLCC-20 footprint; a continuous ground plane minimizes noise coupling on the JTAG signals (TCK, TMS, TDI, TDO) and the serial configuration interface (DCLK, DATA, nCONFIG, CONF_DONE, nSTATUS). Keep the serial configuration traces (DCLK, DATA) short (under 50 mm total length) and impedance-matched to 50 ohm where possible, because these signals run at high frequency during FPGA configuration load. Place the JTAG header on the same board edge as the FPGA's JTAG pins so a single JTAG chain can access both the EPC2L120 and the target FPGA in a single scan.
A common pitfall is connecting the CONF_DONE output directly to VCC instead of using a pull-up resistor to the FPGA's VCCIO supply; CONF_DONE is open-drain and requires an external 10 kohm pull-up to the FPGA's configuration voltage rail, otherwise the FPGA will never see the configuration-complete handshake and will remain stuck in reset. Another common pitfall is using the EPC2L120 on a 5V-only board - this device requires a 3.3V supply and will not function with the legacy EPC1LC20 footprint if the board only has 5V. Always verify the schematic symbol against the Altera Configuration Devices datasheet pinout before committing to PCB layout.
合规信息
Compliance status not stated in verified web data; PLCC-20 packages historically were lead-containing but later Altera revisions may be lead-free. Confirm with manufacturer for specific date-code compliance.
