EPC2LC20 vs EPC1LC20C 对比
详细并排对比 EPC2LC20 出自 Altera 和 EPC1LC20C 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2LC20 | EPC1LC20C |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | Memory ICs | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.20 | $7.40 |
| 存储器类型 | Non-volatile configuration PROM | Serial Configuration Flash |
| 存储容量 | 1.6 Mbit | 1 Mbit (1,048,576 bits) |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| 封装 | 20-pin PLCC (J-lead, 9x9 mm) | 20-pin LCC (Leadless Chip Carrier) |
| 安装类型 | Surface Mount | Surface Mount (ceramic) |
| 工作温度 | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | -40C to +85C (industrial) |
| RoHS 状态 | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| 接口 | — | Serial (DATA/DCLK) + JTAG (IEEE 1149.1) |
| 电源电压 | — | 3.3 V or 5.0 V |
| Programmability | — | In-system via JTAG |
| Cascading Support | — | Yes (nCS, CS pins) |
| Compatible FPGA Families | — | FLEX 10K, ACEX 1K, APEX 20K |
| JTAG Pins | — | TCK, TMS, TDI, TDO |
| Configuration Mode | — | Slave-serial (FPGA-master) |
| MSL 等级 | — | MSL3 (ceramic, floor life 168 hours) |