EPC2LC20ES vs EPC2LC20NU 对比

详细并排对比 EPC2LC20ES 出自 Intel 和 EPC2LC20NU 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2LC20ES EPC2LC20NU
品牌 Intel Altera
分类 Memory ICs Memory ICs
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $5.85 $8.20
存储器类型 Configuration PROM (Non-volatile) —
存储容量 1.6 Mbit —
Target Device SRAM-based FPGAs and LUT devices —
接口 Serial (DCLK/DATA) with JTAG ISP —
Operating Voltage 3.3 V and 5.0 V tolerant —
JTAG Standard IEEE Std. 1149.1 compliant —
In-System Programmability Yes (via built-in JTAG) —
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant —
Configuration Modes Serial and parallel supported —
封装 20-PLCC (J-lead, 9x9 mm) 20-pin J-lead PLCC (9x9 mm)
安装类型 Surface Mount / Through-Hole (PLCC socket) Surface Mount
引脚数量 20 —
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS 状态 Compliant (ES suffix denotes lead-free industrial) —
Programming Interface JTAG (4-wire: TDI/TDO/TMS/TCK) —
Manufacturer Intel (formerly Altera) —
功能 — In-System Programmable Configuration PROM
Memory Density — 1.6 Mbit
FPGA Interface — Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF)
Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Tolerance — 5 V tolerant inputs (per datasheet, except JTAG pins)
Programming Method — In-system via IEEE 1149.1 JTAG
JTAG Support — Yes (IEEE Std 1149.1 boundary-scan compliant)
Cascade Support — Yes - daisy-chain for larger bitstreams
Minimum DC Input — -0.3 V (inputs may undershoot to -2.0 V for <20 ns)
Maximum Overshoot — 7.0 V for <100 mA and <20 ns
Lead-Free / RoHS — Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free)
Compatibility — Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration)

数据手册与资源

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