EPC2LS20U vs EPC1LC20 对比
详细并排对比 EPC2LS20U 出自 Altera 和 EPC1LC20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPC2LS20U | EPC1LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | Memory ICs | Memory ICs |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.25 | $7.95 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| 接口 | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| 封装 | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-leaded, surface mount) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| 工作温度 | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: Operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| MSL 等级 | [DATA_NEEDED: MSL Level] | — |
| Compliance | RoHS (Pb-free per U suffix) | — |
| 存储器类型 | — | Non-volatile configuration memory (Flash/EPROM) |
| Memory Capacity | — | 1 Mbit (1,048,576 bits) |
| 接口类型 | — | Serial configuration interface |
| Maximum DCLK Frequency | — | 8 MHz |
| 电源电压 | — | 3.3 V or 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | — | 5.0 V and 3.3 V ISP |
| Configuration Mode | — | Serial, multi-device daisy-chain capable |
| 引脚数量 | — | 20 |
| 安装类型 | — | Surface Mount |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |
| JTAG Pins | — | TCK, TMS, TDI, TDO |