EPC2LS20U vs EPC1LC20 Comparaison
Comparaison détaillée côte à côte de EPC2LS20U par Altera et EPC1LC20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LS20U | EPC1LC20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,25 | $7,95 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Interface | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Boîtier | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-leaded, surface mount) |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| Température de fonctionnement | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: Operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| Niveau MSL | [DATA_NEEDED: MSL Level] | — |
| Compliance | RoHS (Pb-free per U suffix) | — |
| Type de mémoire | — | Non-volatile configuration memory (Flash/EPROM) |
| Memory Capacity | — | 1 Mbit (1,048,576 bits) |
| Type d'interface | — | Serial configuration interface |
| Maximum DCLK Frequency | — | 8 MHz |
| Tension d'alimentation | — | 3.3 V or 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 / JTAG) |
| Programmable Voltage | — | 5.0 V and 3.3 V ISP |
| Configuration Mode | — | Serial, multi-device daisy-chain capable |
| Nombre de broches | — | 20 |
| Type de montage | — | Surface Mount |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |
| JTAG Pins | — | TCK, TMS, TDI, TDO |