EPC2TC32U vs EPC2TC32-U-CAF48 对比

详细并排对比 EPC2TC32U 出自 Altera 和 EPC2TC32-U-CAF48 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC2TC32U EPC2TC32-U-CAF48
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 有效
库存状态 有库存 有库存
单价(USD) $5.85 $9.95
功能 Serial Configuration Device for SRAM-based LUT FPGAs In-system programmable configuration PROM
存储容量 1.6 Mbit 1.6 Mb
Configuration Interface Altera Passive Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) —
JTAG Support Yes (IEEE 1149.1 boundary-scan, ISP) —
电源电压 3.0 V to 3.6 V or 4.75 V to 5.25 V 3.3 V
工作温度 -40 C to +85 C -40C to +85C (industrial, per data sheet)
封装 32-pin QFP (CAF48, lead-free) 32-TQFP (7x7 mm)
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL level] —
RoHS 状态 Compliant (lead-free / RoHS per distributor data) [DATA_NEEDED: RoHS status]
Lead-Free Finish Yes (U suffix) —
Supported FPGA Families Altera Stratix, Cyclone, APEX, ACEX, Mercury, Excalibur —
Configuration Mode Passive Serial (PS), JTAG —
Configuration Time [DATA_NEEDED: typical configuration time] —
Programming Cycles [DATA_NEEDED: minimum program/erase cycles] —
Data Retention [DATA_NEEDED: minimum data retention years] —
接口 — Serial synchronous (Altera FPGA configuration)
Programming Interface — IEEE 1149.1 JTAG
Control Pins — OE, nCS, DCLK
Cascadable — Yes (DATA output supports daisy-chain)
Storage Technology — EPROM
引脚数量 — 32
DC Input Min — -0.3 V
DC Input Overshoot — 7.0 V for <100 mA, <20 ns
DC Input Undershoot — -2.0 V for <100 mA, <20 ns
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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