EPC4QC100N vs EPC4QC1C00N 对比

详细并排对比 EPC4QC100N 出自 Intel 和 EPC4QC1C00N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC4QC100N EPC4QC1C00N
品牌 Intel Altera
分类 Memory ICs FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $8.10 $9.10
存储器类型 Flash (NOR, configuration PROM) —
存储容量 4 Mbit (4,194,304 bits) —
Programmable Type In System Programmable (ISP) —
Configuration Interface Serial / Parallel / JTAG (IEEE 1149.1) —
Maximum DCLK Frequency 66.7 MHz —
On-Chip Decompression Yes —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V (3.3 V typical)
Typical Supply Voltage 3.3 V —
工作温度 0 C to 70 C (commercial) -40 C to +85 C (industrial)
封装 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (QFP-100)
Package Dimensions 20 x 14 mm —
Pin Pitch 0.65 mm —
安装类型 Surface Mount —
Packaging Tray —
Lead Free / RoHS Yes (per chipdig datasheet excerpt) —
Family EPC4 Enhanced Configuration Device —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Device Family — Enhanced Configuration Device (EPC4)
Memory Density — 4 Mbit (4,194,304 bits)
I/O Voltage Tolerance — 3.3 V / 5 V tolerant
Interface to FPGA — Serial DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE
Configuration Data Width — 4-bit multiplexed on single DATA pin
In-System Programming — JTAG (IEEE 1149.1)
Programming Voltage — On-chip generated, no external VPP
Page Mode — Yes, multi-page storage supported
Target FPGA Families — Stratix, Cyclone, APEX, Mercury, ACEX
Configuration Clock (DCLK) — [DATA_NEEDED: DCLK max frequency]
MSL 等级 — 3 (per JEDEC J-STD-020)
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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