EPF6016QC208-3N vs EPF6016QC208 对比

详细并排对比 EPF6016QC208-3N 出自 Altera 和 EPF6016QC208 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPF6016QC208-3N EPF6016QC208
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $20.40 $23.50
Family FLEX 6000 FLEX 6000
Logic Elements / Cells 1,320 cells —
Usable Gates 16,000 gates —
Logic Array Blocks (LABs) 132 132 LABs (10 LEs per LAB)
Maximum User I/O 171 171 I/O pins
Maximum Operating Frequency 125 MHz (internal, per family spec) —
Internal Toggle Rate Up to 172 MHz —
Process Technology 0.42 µm CMOS, SRAM-based 0.42 um CMOS (SRAM-based)
Core Supply Voltage (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V —
封装 208-pin PQFP (Power Quad Flat Pack) PQFP-208 (Plastic Quad Flat Pack)
安装类型 Surface Mount Surface Mount
Configuration Method Serial configuration EPROM or JTAG (ByteBlaster) —
工作温度 0 °C to +85 °C (commercial) 0C to 70C (commercial)
RoHS 状态 unknown Non-compliant (legacy 5V PQFP, contains lead)
Lifecycle Obsolete (Altera FLEX 6000 family EOL) —
Equivalent Gates — 16,000 gates
Logic Cells / Logic Elements (LEs) — 1,320 LEs
Maximum Internal Frequency — 125 MHz
Supply Voltage (VCCINT) — 5.0 V
I/O Standard Support — 5.0 V CMOS (3.3 V VCCIO supported)
Configuration Memory — SRAM (volatile, requires external config EPROM)
引脚数量 — 208 pins
JTAG Support — IEEE Std 1149.1 boundary scan
Configuration Device Compatibility — EPC1, EPC2 (legacy Altera config PROMs)

数据手册与资源

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