EPM3064ALC44-10 vs EPM3064ALC44-10N 对比
详细并排对比 EPM3064ALC44-10 出自 Altera 和 EPM3064ALC44-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N Obsolete规格对比
| 参数 | EPM3064ALC44-10 | EPM3064ALC44-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.12 | $4.25 |
| Family | MAX 3000A | — |
| Logic Elements / Macrocells | 64 macrocells | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1,250 | 1,250 |
| Maximum User I/O Pins | 34 | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 192.3 MHz | — |
| Maximum Operating Frequency (fMAX) | [DATA_NEEDED: fMAX internal] | — |
| 封装 | 44-PLCC (J-Lead) | 44-pin PLCC (LC44) |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Programmability | In-system programmable (JTAG IEEE 1149.1) | — |
| MultiVolt I/O | 2.5V / 3.3V / 5.0V interface compatible | — |
| 工作温度 | 0°C to +70°C (commercial) | [DATA_NEEDED: commercial / industrial grade] |
| RoHS 状态 | Compliant (lead-free L suffix indicates Pb-free package) | Compliant |
| 安装类型 | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| I/O Bank Voltage (VCCIO) | — | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |