EPM3064ALC44-10 vs EPM3064ALC44-10N Comparison
Detailed side-by-side comparison of EPM3064ALC44-10 by Altera and EPM3064ALC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpecification Comparison
| Parameter | EPM3064ALC44-10 | EPM3064ALC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.12 | $4.25 |
| Family | MAX 3000A | β |
| Logic Elements / Macrocells | 64 macrocells | β |
| Number of Logic Array Blocks (LABs) | 4 | β |
| Usable Gates | 1,250 | 1,250 |
| Maximum User I/O Pins | 34 | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 192.3 MHz | β |
| Maximum Operating Frequency (fMAX) | [DATA_NEEDED: fMAX internal] | β |
| Package | 44-PLCC (J-Lead) | 44-pin PLCC (LC44) |
| Process Technology | 0.30 Β΅m CMOS EEPROM | β |
| Programmability | In-system programmable (JTAG IEEE 1149.1) | β |
| MultiVolt I/O | 2.5V / 3.3V / 5.0V interface compatible | β |
| Operating Temperature | 0Β°C to +70Β°C (commercial) | [DATA_NEEDED: commercial / industrial grade] |
| RoHS Status | Compliant (lead-free L suffix indicates Pb-free package) | Compliant |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Product Family | β | MAX 3000A |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 64 |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 34 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| I/O Bank Voltage (VCCIO) | β | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | β | Yes (per I/O pin) |
| Output Slew-Rate Control | β | Programmable |