EPM3064AT100-10N vs EPM3064ATC100-10 对比
详细并排对比 EPM3064AT100-10N 出自 Altera 和 EPM3064ATC100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd规格对比
| 参数 | EPM3064AT100-10N | EPM3064ATC100-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.45 | $2.85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1,250 | — |
| User I/O Pins | 66 | 34 |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Bank Voltage | 3.3 V | — |
| 5 V Tolerant Inputs | Yes (via clamping diodes) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1) with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | IEEE Std. 1149.1 compliant | — |
| 封装 | TQFP-100 (T100), 14 mm x 14 mm | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Operating Temperature (Commercial) | 0C to +70C | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free finish] | — |
| Logic Gates | — | 1250 gates |
| Logic Array Blocks | — | 2 |
| Propagation Delay (tPD) | — | 10 ns |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant |
| Global Clock Signals | — | 2 (with optional inversion) |
| Output Enable Signals | — | 6 or 10 pin- or logic-driven |
| Output Slew-Rate Control | — | Programmable |
| Operating Temperature Grade | — | Commercial |
| MultiVolt I/O Support | — | 1.5V / 1.8V / 2.5V / 3.3V interfaces |