EPM3064AT100-10N vs EPM3064ATC100-10 Comparison

Detailed side-by-side comparison of EPM3064AT100-10N by Altera and EPM3064ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064AT100-10N

EPM3064AT100-10N - MAX 3000A CPLD, 64 Macrocells, TQFP-100 | Intel

EPM3064AT100-10N Nrnd

Specification Comparison

Parameter EPM3064AT100-10N EPM3064ATC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $5.45 $2.85
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 64 64
Logic Array Blocks (LABs) 4 β€”
Usable Gates 1,250 β€”
User I/O Pins 66 34
Speed Grade -10 (10 ns pin-to-pin delay) β€”
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Bank Voltage 3.3 V β€”
5 V Tolerant Inputs Yes (via clamping diodes) β€”
Configuration Memory EEPROM (non-volatile) β€”
Programming Interface JTAG (IEEE Std. 1149.1) with pin-locking β€”
ISP Compliance IEEE Std. 1532 β€”
Boundary-Scan Test (BST) IEEE Std. 1149.1 compliant β€”
Package TQFP-100 (T100), 14 mm x 14 mm TQFP-100 (100-pin Thin Quad Flat Pack)
Operating Temperature (Commercial) 0C to +70C β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free finish] β€”
Logic Gates β€” 1250 gates
Logic Array Blocks β€” 2
Propagation Delay (tPD) β€” 10 ns
Process Technology β€” CMOS EEPROM
In-System Programmability β€” IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals β€” 2 (with optional inversion)
Output Enable Signals β€” 6 or 10 pin- or logic-driven
Output Slew-Rate Control β€” Programmable
Operating Temperature Grade β€” Commercial
MultiVolt I/O Support β€” 1.5V / 1.8V / 2.5V / 3.3V interfaces

Datasheets & Resources

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