EPM3128AFI256-10N vs EPM3128ATC100-10NS 对比

详细并排对比 EPM3128AFI256-10N 出自 Altera 和 EPM3128ATC100-10NS 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128AFI256-10N EPM3128ATC100-10NS
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $9.75 $6.50
Family MAX 3000A MAX 3000A
Logic Density 2.5K gates —
Macro Cells 128 128
User I/Os 98 80
Speed Grade -10 (10 ns pin-to-pin) —
Propagation Delay (tPD) 10 ns —
Counter Frequency (max) 227.3 MHz —
Logic Family CMOS, EEPROM-based —
Supply Voltage (Core) 3.3 V —
I/O Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt) —
In-System Programmability Yes (JTAG / IEEE 1149.1) —
封装 256-ball FineLine BGA (FBGA-256) TQFP-100
工作温度 -40C to +85C (industrial, per 'I' suffix) [DATA_NEEDED: operating temperature range]
引脚数量 256 100
RoHS 状态 Compliant [DATA_NEEDED: RoHS compliance status]
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
PCI Compliance PCI Local Bus Spec Rev 2.2 —
Device Type — CPLD (Complex Programmable Logic Device)
Pin-to-Pin Logic Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 3.3 V or 2.5 V (5.0 V-tolerant inputs)
Logic-Level Compatibility — 5.0 V, 3.3 V, 2.5 V
Programmability — In-system (ISP), IEEE Std. 1532
Boundary Scan — IEEE 1149.1 JTAG
安装类型 — Surface Mount
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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