EPM3128ATC100-7N vs EPM3128ATC100-10N 对比

详细并排对比 EPM3128ATC100-7N 出自 Intel 和 EPM3128ATC100-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATC100-7N EPM3128ATC100-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $3.52 $5.20
Family MAX 3000A MAX 3000A
Macro Cells 128 128
Usable Gates Up to 10,000 2500
Number of I/Os 80 —
Number of Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Propagation Delay (tPD) 7.5 ns 10 ns
Counter Frequency (max) 227.3 MHz —
Supply Voltage - Core 3.3 V —
I/O Interface Levels 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) —
In-System Programmability Yes (IEEE 1532 / JTAG) —
Program Memory Type EEPROM (non-volatile) —
工作温度 0C to +70C (Commercial) 0 °C to +70 °C (commercial)
封装 TQFP-100 (100-pin TQFP, fine-line BGA-256 noted in third-party listings) 100-pin TQFP (14 x 14 x 1.0 mm)
安装类型 Surface Mount Surface Mount
Logic Family CMOS —
Speed Grade -7 —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant
Product Type — CPLD (Complex Programmable Logic Device)
Number of I/O — 80
Logic Elements / Blocks — 8 LABs (16 macrocells each)
Maximum Internal Frequency (fMAX) — 98 MHz
Supply Voltage VCCINT — 3.3 V
I/O Bank Voltage VCCIO — 3.3 V or 2.5 V (selectable)
Configuration Memory — CMOS EEPROM (non-volatile, instant-on)
In-System Programming — IEEE Std. 1532-compliant ISP via JTAG
Lead-Free — Yes
MSL 等级 — 3 (per JEDEC J-STD-020)

数据手册与资源

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