EPM3128ATI144-5N vs EPM3128ATI144-10 对比

详细并排对比 EPM3128ATI144-5N 出自 Altera 和 EPM3128ATI144-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128ATI144-5N EPM3128ATI144-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $10.50 $10.85
Family MAX 3000A MAX 3000A
Logic Gates 2,500 gates —
Macro Cells 128 128
User I/Os 96 98
Maximum Operating Frequency 192.3 MHz —
Pin-to-Pin Propagation Delay (tPD) 5.0 ns —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V nominal) 3.3 V
I/O Standard LVCMOS / LVTTL (5.0 V tolerant inputs) —
Programming Interface JTAG (IEEE 1149.1 BST) - in-system IEEE 1149.1 JTAG (ISP)
Process Technology 0.30 um CMOS EEPROM —
Configuration Memory Non-volatile on-chip EEPROM —
封装 TQFP-144 (20x20 mm, 0.5 mm pitch) TQFP-144 (FINE LINE)
安装类型 Surface Mount Surface Mount (Gull-Wing TQFP)
工作温度 -40C to +85C (industrial) -40C to +85C (Industrial)
MSL 等级 3 (168 hours) —
RoHS 状态 [DATA_NEEDED: RoHS status] Compliant (lead-free TQFP)
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 2,500
Logic Array Blocks (LABs) — 8
引脚数量 — 144
Pin-to-Pin Delay — 10 ns (speed grade -10)
Counter Frequency — 98 MHz typical
Logic Family — CMOS, EEPROM-based
PCI Compliance — PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10)

数据手册与资源

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