EPM3256AFC256-10N vs EPM3256AFC256-10 对比
详细并排对比 EPM3256AFC256-10N 出自 Altera 和 EPM3256AFC256-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ 最后一次采购规格对比
| 参数 | EPM3256AFC256-10N | EPM3256AFC256-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $25.95 | $19.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 gates | 5,000 |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| 封装 | 256-pin FineLine BGA | 256-ball FBGA (Fine-Line BGA) |
| Logic Family | CMOS | CMOS (EEPROM-based) |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| 工作温度 | 0 C to 70 C (commercial) | 0°C to +70°C (Commercial) |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 (16 macrocells each) |
| Maximum User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| In-System Programmability | — | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |
| 安装类型 | — | Surface Mount |
| RoHS 状态 | — | [DATA_NEEDED: RoHS compliance status] |