EPM3512AFC256-10N vs EPM3512AFC256-18 对比

详细并排对比 EPM3512AFC256-10N 出自 Altera 和 EPM3512AFC256-18 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-10N EPM3512AFC256-18
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $43.22 $17.20
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10000 —
User I/O Pins 208 —
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] 16
Operating Frequency (fMAX) [DATA_NEEDED: fMAX MHz] —
Pin-to-Pin Delay (tPD) 10 ns —
Setup Time (tSU) 4.5 ns —
VCCINT (Core Supply) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) 3.3 V or 2.5 V 2.5 V or 3.3 V (MultiVolt)
Technology CMOS EEPROM-based, non-volatile —
Operating Temperature (Commercial) 0 C to +70 C —
封装 256-ball FBGA (17 mm x 17 mm) 256-ball FineLine BGA (FCBGA)
ISP Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: not specified in retrieved data]
Maximum User I/O Pins — 212
Pin-to-Pin Delay (tPD1) — 18 ns
Global Clock Networks — 4
工作温度 — [DATA_NEEDED: industrial/commercial grade]
Programming Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
Ball Pitch — 1.0 mm

数据手册与资源

浏览全部产品 创建 BOM 获取报价