EPM3512AFC256-18 vs EPM3256AFC256-7 对比

详细并排对比 EPM3512AFC256-18 出自 Altera 和 EPM3256AFC256-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-18 EPM3256AFC256-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $17.20 $12.10
Family MAX 3000A MAX 3000A
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 —
Pin-to-Pin Delay (tPD1) 18 ns —
Global Clock Networks 4 —
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) —
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) —
工作温度 [DATA_NEEDED: industrial/commercial grade] 0 °C to 70 °C (Commercial)
Programming Technology EEPROM (non-volatile) —
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) —
封装 256-ball FineLine BGA (FCBGA) FBGA-256 (FineLine BGA), 256 balls
Ball Pitch 1.0 mm —
RoHS 状态 [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS compliance status]
安装类型 Surface Mount —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 256
Usable Gates — 10,000
User I/Os — 161
Pin-to-Pin Logic Delay — 4.5 ns (max)
Counter Frequency — 227.3 MHz (max)
Propagation Delay (tpd) — 10 ns
Core Voltage — 3.3 V
I/O Compatibility — 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
Process Technology — CMOS EEPROM, 0.30 µm
In-System Programmability — IEEE Std. 1532-compliant 3.3-V ISP
Boundary-Scan Test — JTAG (IEEE 1149.1)
Speed Grade — -7

数据手册与资源

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