EPM3512AFC256-22 vs EPM3512AFC256-21 对比

详细并排对比 EPM3512AFC256-22 出自 Intel 和 EPM3512AFC256-21 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-22 EPM3512AFC256-21
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $16.10 $18.75
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) —
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) —
封装 FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) FBGA-256 (FineLine BGA)
安装类型 Surface Mount (BGA) Surface Mount (BGA)
工作温度 [DATA_NEEDED: operating temperature grade] -40C to +85C (industrial)
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Device Family — MAX 3000A
Logic Elements / Macrocells — 512 macrocells
Usable Gates — 10,000
Maximum Operating Frequency — 87 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) — [DATA_NEEDED: maximum user I/O pin count]
Programming Interface — JTAG / IEEE Std. 1532 ISP
存储器类型 — Non-volatile EPROM/EEPROM cell array
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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