EPM3512AFC256-22 vs EPM3512AFC256-21 Comparison

Detailed side-by-side comparison of EPM3512AFC256-22 by Intel and EPM3512AFC256-21 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-22 EPM3512AFC256-21
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $16.10 $18.75
Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 β€”
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 208 (typical for FC256 package) β€”
Speed Grade -22 (tPD ~22 ns) β€”
Propagation Delay (tPD) 22 ns β€”
Supply Voltage VCCINT 3.3 V β€”
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) β€”
In-System Programming IEEE Std. 1532-compliant ISP via JTAG β€”
Configuration Memory On-chip EEPROM (non-volatile) β€”
Package FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) FBGA-256 (FineLine BGA)
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
Operating Temperature [DATA_NEEDED: operating temperature grade] -40C to +85C (industrial)
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Device Family β€” MAX 3000A
Logic Elements / Macrocells β€” 512 macrocells
Usable Gates β€” 10,000
Maximum Operating Frequency β€” 87 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) β€” [DATA_NEEDED: maximum user I/O pin count]
Programming Interface β€” JTAG / IEEE Std. 1532 ISP
Memory Type β€” Non-volatile EPROM/EEPROM cell array
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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