EPM3512AFC256-7 vs EPM3512AFI256-7 对比
详细并排对比 EPM3512AFC256-7 出自 Intel 和 EPM3512AFI256-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ 最后一次采购规格对比
| 参数 | EPM3512AFC256-7 | EPM3512AFI256-7 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $58.40 | $15.95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| User I/O Pins | 212 | 208 |
| Usable Gates | 10,000 | 10,000 |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | — |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| 封装 | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | — |
| 工作温度 | [DATA_NEEDED: operating temperature grade] | — |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from data] |
| Configuration Memory | Non-volatile EEPROM | — |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX value] |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| In-System Programmability | — | IEEE Std. 1532 compliant via JTAG |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature (Industrial) | — | -40 °C to +85 °C |