EPM3512AFI256-10 vs EPM3512AFC256-7N 对比

详细并排对比 EPM3512AFI256-10 出自 Intel 和 EPM3512AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFI256-10 EPM3512AFC256-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $18.75 $61.00
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Equivalent Gates 10,000 —
Macrocells 512 512
User I/Os 208 208
Pin-to-Pin Logic Delay (tPD) 4.5 ns —
Maximum Counter Frequency 227.3 MHz —
Propagation Delay 7.5 ns (max, per chipdig summary) —
Core Voltage 3.3 V —
MultiVolt I/O Levels 5.0 V / 3.3 V / 2.5 V —
Process Technology CMOS EEPROM CMOS EEPROM, 0.30 um
In-System Programmability Yes, IEEE Std. 1532 (3.3 V ISP) IEEE Std. 1532 compliant
封装 FBGA-256 (FineLine BGA, 256 balls) 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
工作温度 0C to +70C (commercial) 0 C to 70 C (commercial)
Logic Family CMOS —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
电源电压 3.3 V (core); MultiVolt I/O to 5.0 V —
Usable Gates — 10,000
Logic Blocks — 16 (32 macrocells each)
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
Programming Interface — JTAG (IEEE 1149.1)
安装类型 — Surface Mount

数据手册与资源

浏览全部产品 创建 BOM 获取报价