EPM5032DI-25 vs EPM5032DI-20 对比
详细并排对比 EPM5032DI-25 出自 Altera 和 EPM5032DI-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032DI-25 | EPM5032DI-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $18.20 | $8.75 |
| Family | MAX 5000 | MAX 5000 (Altera legacy EPLD) |
| Device Type | UV-erasable Programmable Logic Device (PLD) | — |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | CMOS PAL-type EPLD with PIA |
| Macrocells | 32 | 32 |
| Product Terms | 320 | 320 (maximum) |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| 电源电压 | 5 V | — |
| Process Technology | CMOS | — |
| 封装 | Ceramic DIP, windowed (UV-erasable) | Ceramic DIP-20 (windowed, UV-erasable) |
| 引脚数量 | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| 工作温度 | 0C to +70C (commercial) | Industrial (per 'I' suffix) |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | Altera MAX+PLUS II (legacy) |
| RoHS 状态 | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| Flip-Flops | — | 16 (one per macrocell) |
| 最大时钟频率 | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |