EPM5032JC25 vs EPM5032DC-25 对比

详细并排对比 EPM5032JC25 出自 Altera 和 EPM5032DC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032JC25 EPM5032DC-25
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $23.95 $3.55
Family MAX 5000 —
Device EPM5032 —
Logic Elements 32 macrocells —
Propagation Delay (tPD) 25 ns —
Maximum Internal Frequency 62.5 MHz —
Product Terms 320 —
Flip-Flops 32 —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Inputs to Array 24 —
输出数量 16 —
Architecture PAL-type macrocells with global Programmable Interconnect Array (PIA) PAL-Type, Single-LAB, 32-Macrocell
Technology CMOS EPROM, UV-erasable (windowed) / OTP —
电源电压 5 V (TTL-level I/O) —
封装 28-pin PLCC (JC) CDIP-28 (Windowed Ceramic DIP-28)
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 32
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
工作温度 — [DATA_NEEDED: operating temperature range]
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

数据手册与资源

浏览全部产品 创建 BOM 获取报价