EPM5032JC25 vs EPM5032DC-25 비교

다음의 상세 나란히 비교: EPM5032JC25 제조: Altera 및 EPM5032DC-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5032JC25 EPM5032DC-25
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $23.95 $3.55
Family MAX 5000 —
Device EPM5032 —
Logic Elements 32 macrocells —
Propagation Delay (tPD) 25 ns —
Maximum Internal Frequency 62.5 MHz —
Product Terms 320 —
Flip-Flops 32 —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Inputs to Array 24 —
출력 수 16 —
Architecture PAL-type macrocells with global Programmable Interconnect Array (PIA) PAL-Type, Single-LAB, 32-Macrocell
Technology CMOS EPROM, UV-erasable (windowed) / OTP —
공급 전압 5 V (TTL-level I/O) —
패키지 28-pin PLCC (JC) CDIP-28 (Windowed Ceramic DIP-28)
실장 유형 Surface Mount —
RoHS 상태 [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 32
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
동작 온도 — [DATA_NEEDED: operating temperature range]
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

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