EPM5032JC25 vs EPM5032DC-25 Comparison

Detailed side-by-side comparison of EPM5032JC25 by Altera and EPM5032DC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032JC25 EPM5032DC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 5000 —
Device EPM5032 —
Logic Elements 32 macrocells —
Propagation Delay (tPD) 25 ns —
Maximum Internal Frequency 62.5 MHz —
Product Terms 320 —
Flip-Flops 32 —
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Total Inputs to Array 24 —
Number of Outputs 16 —
Architecture PAL-type macrocells with global Programmable Interconnect Array (PIA) PAL-Type, Single-LAB, 32-Macrocell
Technology CMOS EPROM, UV-erasable (windowed) / OTP —
Supply Voltage 5 V (TTL-level I/O) —
Package 28-pin PLCC (JC) CDIP-28 (Windowed Ceramic DIP-28)
Mounting Type Surface Mount —
RoHS Status [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 32
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Operating Temperature — [DATA_NEEDED: operating temperature range]
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

Datasheets & Resources

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