EPM5032SC-20 vs EPM5032PC-15 对比

详细并排对比 EPM5032SC-20 出自 Altera 和 EPM5032PC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032SC-20 EPM5032PC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $8.75 $8.10
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable PLD)
Family MAX 5000 —
Macrocells 32 —
Dedicated Inputs 7 7
I/O Pins 16 —
Outputs 16 —
Propagation Delay (tPD) 20 ns 15 ns
Speed Grade -20 (20 ns) 15 (15 ns tPD)
Architecture PAL-type, CMOS, UV-erasable —
Interconnect Programmable Interconnect Array (PIA) —
封装 20-pin SOIC (Small Outline) 28-pin PDIP (PC suffix = windowed CerDIP)
工作温度 0 °C to +70 °C (commercial grade) 0C to +70C (commercial)
安装类型 Surface Mount Through-Hole (DIP)
电源电压 [DATA_NEEDED: VCC typical range] —
Technology CMOS EPROM cell —
Programmability One-time programmable (windowless SOIC) —
RoHS 状态 [DATA_NEEDED: RoHS status not confirmed in verified data] Non-compliant (CerDIP window, contains Be)
Device Family — MAX 5000
Macro Cells — 32
Usable Gates — 600
Logic Elements / LABs — 1 LAB (4 macrocells per group)
Maximum Internal Frequency — 76.9 MHz (some sources list 83.3 MHz)
Operating Voltage (VCC) — 5 V (typ.)
Technology Node — 0.8 micron CMOS
Configuration Memory — UV-Erasable EPROM
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Pin/Package Suffix — PC = Windowed Ceramic DIP
Programming Tool — Altera Logic Programmer + MAX+plus II
Lead-Free — No

数据手册与资源

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