EPM5032SC-20 vs EPM5032PC-15 Comparison

Detailed side-by-side comparison of EPM5032SC-20 by Altera and EPM5032PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032SC-20 EPM5032PC-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.75 $8.10
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable PLD)
Family MAX 5000 β€”
Macrocells 32 β€”
Dedicated Inputs 7 7
I/O Pins 16 β€”
Outputs 16 β€”
Propagation Delay (tPD) 20 ns 15 ns
Speed Grade -20 (20 ns) 15 (15 ns tPD)
Architecture PAL-type, CMOS, UV-erasable β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Package 20-pin SOIC (Small Outline) 28-pin PDIP (PC suffix = windowed CerDIP)
Operating Temperature 0 Β°C to +70 Β°C (commercial grade) 0C to +70C (commercial)
Mounting Type Surface Mount Through-Hole (DIP)
Supply Voltage [DATA_NEEDED: VCC typical range] β€”
Technology CMOS EPROM cell β€”
Programmability One-time programmable (windowless SOIC) β€”
RoHS Status [DATA_NEEDED: RoHS status not confirmed in verified data] Non-compliant (CerDIP window, contains Be)
Device Family β€” MAX 5000
Macro Cells β€” 32
Usable Gates β€” 600
Logic Elements / LABs β€” 1 LAB (4 macrocells per group)
Maximum Internal Frequency β€” 76.9 MHz (some sources list 83.3 MHz)
Operating Voltage (VCC) β€” 5 V (typ.)
Technology Node β€” 0.8 micron CMOS
Configuration Memory β€” UV-Erasable EPROM
Bidirectional I/O Pins β€” 16
Total Array Inputs β€” 24
Pin/Package Suffix β€” PC = Windowed Ceramic DIP
Programming Tool β€” Altera Logic Programmer + MAX+plus II
Lead-Free β€” No

Datasheets & Resources

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