EPM5064LC-2 vs EPM5064JC-2 对比
详细并排对比 EPM5064LC-2 出自 Altera 和 EPM5064JC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5064LC-2 | EPM5064JC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $8.40 | $23.10 |
| Device Family | MAX 5000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Logic Elements per LAB | 16 | — |
| Number of Inputs | 36 (7 dedicated + 28 I/O) | — |
| Number of I/O Pins | 28 | — |
| Number of Flip-Flops | 28 | — |
| Propagation Delay (tPD) | 45 ns | 45 ns |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS, OTP EPROM (UV-erasable base) | — |
| Programmable Polarity | Yes | — |
| Programmable Output Enable | Yes, per macrocell | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (4.75 V to 5.25 V) |
| 工作温度 | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] | [DATA_NEEDED: commercial or industrial grade] |
| 封装 | PLCC-44 (J-Lead, plastic) | 28-pin CLCC (J-lead, ceramic, windowed) |
| 安装类型 | Surface Mount | — |
| RoHS 状态 | [DATA_NEEDED: not specified in source] | — |
| Programming Method | Altera byte-wide / JTAG programmer | UV-erase + EPROM programmer (not ISP) |
| Family | — | MAX 5000 |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Usable Gates | — | 1250 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 28 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Technology | — | CMOS, UV-erasable EPROM |
| Compliance | — | RoHS status unknown (ceramic/J-lead windowed part, legacy product) |