EPM5064LC vs EPM5064LC-2 对比

详细并排对比 EPM5064LC 出自 Altera 和 EPM5064LC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5064LC EPM5064LC-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $7.10 $8.40
Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Programming Type OTP (One-Time-Programmable, UV-erasable EPROM) —
Macro Cells 64 —
Usable Gates 1.25K —
Logic Array Blocks (LABs) 4 4
Propagation Delay (tPD) 55 ns 45 ns
Total Inputs 36 (7 dedicated + 29 I/O) —
I/O Pins 28 bidirectional + 4 dedicated input —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5 V nominal)
工作温度 0C to +70C (Commercial) -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
封装 PLCC-44 (LCC-44, J-lead) PLCC-44 (J-Lead, plastic)
Process Technology CMOS EPROM CMOS, OTP EPROM (UV-erasable base)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant] [DATA_NEEDED: not specified in source]
Lead Free [DATA_NEEDED: lead-free status] —
Device Family — MAX 5000
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
Logic Elements per LAB — 16
Number of Inputs — 36 (7 dedicated + 28 I/O)
Number of I/O Pins — 28
Number of Flip-Flops — 28
Maximum Internal Frequency — 40 MHz
Programmable Polarity — Yes
Programmable Output Enable — Yes, per macrocell
Programming Method — Altera byte-wide / JTAG programmer

数据手册与资源

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