EPM5128GC-1 vs EPM5128GC 对比
详细并排对比 EPM5128GC-1 出自 Altera 和 EPM5128GC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5128GC-1 | EPM5128GC |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $18.95 | $19.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Dedicated Inputs | 7 | — |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | — |
| 封装 | PGA-96+ (Pin Grid Array, ceramic windowed) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 工作温度 | -40C to +85C (industrial) | — |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | [DATA_NEEDED: RoHS compliance] |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |
| Configuration Memory | — | Non-volatile UV-EPROM (windowed ceramic) |
| 安装类型 | — | Through-Hole (PGA socket required) |