EPM5128GC2 vs EPM5128GC-2 对比

详细并排对比 EPM5128GC2 出自 Altera 和 EPM5128GC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128GC2 EPM5128GC-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $54.00 $8.95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) —
Macro Cells 128 —
Usable Gates 2.5K —
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum Internal Frequency 50 MHz —
Supply Voltage VCC 5 V —
I/O Pins 64 —
Dedicated Inputs 16 —
封装 Ceramic PGA (GC, windowed) —
Programmable Flip-Flop Modes D / T / JK / SR (selectable) —
Architecture AND/OR plane + programmable macro cell + PIA —
Process Technology CMOS EPROM —
Reprogrammability UV-erasable (windowed ceramic package) —
工作温度 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
RoHS 状态 [DATA_NEEDED: RoHS status] —
Configuration Memory On-chip EPROM (no external boot device) Non-volatile, one-time programmable (erasable via UV)
引脚数量 [DATA_NEEDED: total PGA pin count] —
Logic Elements / Gates — 2,500 usable gates
Macrocells — 128
Number of Usable Gates — 2,500
Maximum Operating Frequency — 50 MHz
Propagation Delay (tPD) — Approx. 25 ns (typical, -2 speed grade)
Supply Voltage (VCC) — 5 V (nominal)
Package Type — 68-pin PGA (Pin Grid Array)
Package Code (per Partstack) — WPGA
Number of Terminals — 68
Programming Technology — UV-erasable EPROM
Grade (per Partstack) — COMMERCIAL
Terminal Form — PIN/PEG

数据手册与资源

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