EPM5192GI-1 vs EPM5192LI-1 对比

详细并排对比 EPM5192GI-1 出自 Altera 和 EPM5192LI-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GI-1 EPM5192LI-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $165.00 $16.40
Family MAX 5000 MAX 5000
Device Type Complex Programmable Logic Device (CPLD) EPLD (UV-Erasable/OTP Complex PLD)
Architecture PAL-type, UV-erasable CMOS EEPROM/EPROM-based, non-volatile, instant-on
Macrocells 192 192
User I/O Pins 64 [DATA_NEEDED: user I/O count for JLCC variant]
Dedicated Inputs 7 —
Logic Array Blocks (LABs) 12 —
Propagation Delay (tPD) 25 ns [DATA_NEEDED: tPD in ns at -1 grade]
Maximum Clock Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 5.0 V —
工作温度 -40C to +85C (Industrial) [DATA_NEEDED: industrial vs military range]
封装 84-pin PGA (Pin Grid Array), windowed ceramic —
Configuration Memory UV-EPROM (windowed ceramic PGA) —
Process Technology CMOS CMOS EPROM, UV-erasable
RoHS 状态 unknown (legacy UV-windowed package) [DATA_NEEDED: RoHS status of ceramic LI variant]
Usable Gates — 3,750
Maximum Toggle Frequency — 40 MHz
电源电压 — 5 V
Package Type — JLCC (windowed, ceramic, UV-erasable)
Speed Grade — -1
引脚数量 — [DATA_NEEDED: pin count of LI package]
安装类型 — Surface Mount (JLCC with J-leads)
MSL 等级 — [DATA_NEEDED: MSL level]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)

数据手册与资源

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