EPM5192JC-2 vs EPM5192JC1 对比

详细并排对比 EPM5192JC-2 出自 Altera 和 EPM5192JC1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192JC-2 EPM5192JC1
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $22.50 $48.30
Device Family MAX 5000 —
Product Type UV-erasable Programmable Logic Device (PLD) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Interconnect Programmable Interconnect Array (PIA) —
User I/O Pins 64 —
Dedicated Inputs 7 —
External Clock Inputs 1 —
Propagation Delay (tPD) 45 ns —
最大时钟频率 40 MHz —
Process Technology CMOS 0.5 µm CMOS, UV-erasable EPROM
封装 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) [DATA_NEEDED: exact package from datasheet]
安装类型 Surface Mount [DATA_NEEDED: surface mount or through-hole]
Number of Terminals 84 —
Programming Method UV-erase / EPROM —
工作温度范围 [DATA_NEEDED: operating temperature range] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] unknown
Family — MAX 5000 (MAX 5xxx CPLD)
Manufacturer — Intel (formerly Altera Corporation)
Macro Cells — 192
Usable Gates — 3750
Maximum Operating Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V (nominal)
Propagation Delay (typ) — [DATA_NEEDED: propagation delay in ns]
I/O Pins — [DATA_NEEDED: I/O pin count]
工作温度 — [DATA_NEEDED: operating temp range]
Programming Interface — JTAG-compatible (Altera MAX 5xxx)
Logic Blocks (LABs) — 24 (8 macrocells per LAB)
AEC-Q100 — not_applicable
Lifecycle — Obsolete - last-time-buy stock only at franchised distributors

数据手册与资源

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