EPM5192JC84-1 vs EPM5192GI84 对比

详细并排对比 EPM5192JC84-1 出自 Altera 和 EPM5192GI84 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192JC84-1 EPM5192GI84
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $15.20 $19.80
Device Type UV-Erasable/OTP Complex Programmable Logic Device (CPLD) UV-Erasable / OTP Complex PLD (CPLD)
Family MAX 5000 MAX 5000
Macrocells 192 192
Propagation Delay (tpd) 40 ns (worst case) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V ±5 %) —
Process Technology CMOS EPROM —
Operating Temperature Grade Commercial —
封装 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
JESD-30 Package Code S-CQCC-J84 —
Terminal Form J-BEND PIN/PEG
Package Shape SQUARE SQUARE
安装类型 Surface Mount Through-Hole (PGA socket or PCB pin/peg)
Programmability UV-erasable (window) / OTP in production UV-erasable (windowed) / OTP
Configuration Memory EPROM (non-volatile, instant-on) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
工作温度范围 — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84

数据手册与资源

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