EPM5192JC84-1 vs EPM5192GI84 비교

다음의 상세 나란히 비교: EPM5192JC84-1 제조: Altera 및 EPM5192GI84 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192JC84-1 EPM5192GI84
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $15.20 $19.80
Device Type UV-Erasable/OTP Complex Programmable Logic Device (CPLD) UV-Erasable / OTP Complex PLD (CPLD)
Family MAX 5000 MAX 5000
Macrocells 192 192
Propagation Delay (tpd) 40 ns (worst case) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V ±5 %) —
Process Technology CMOS EPROM —
Operating Temperature Grade Commercial —
패키지 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
JESD-30 Package Code S-CQCC-J84 —
Terminal Form J-BEND PIN/PEG
Package Shape SQUARE SQUARE
실장 유형 Surface Mount Through-Hole (PGA socket or PCB pin/peg)
Programmability UV-erasable (window) / OTP in production UV-erasable (windowed) / OTP
Configuration Memory EPROM (non-volatile, instant-on) —
RoHS 상태 [DATA_NEEDED: RoHS status] [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
동작 온도 범위 — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84

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