EPM5192JI-1 vs EPM5192LI-1 对比
详细并排对比 EPM5192JI-1 出自 Intel 和 EPM5192LI-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192JI-1 | EPM5192LI-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $17.40 | $16.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | EPLD (UV-Erasable/OTP Complex PLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count for JLCC variant] |
| Dedicated Inputs | 7 | — |
| Propagation Delay (tPD) | 55 ns | [DATA_NEEDED: tPD in ns at -1 grade] |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| 封装 | 84-pin JLCC (Windowed ceramic J-lead) | — |
| 工作温度 | Industrial, -40 C to +85 C | [DATA_NEEDED: industrial vs military range] |
| Configuration Memory | UV-erasable EPROM | — |
| Programming Method | External EPROM programmer (via programming hardware) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status of ceramic LI variant] |
| Speed Grade | -1 (slowest grade in EPM5192 family) | -1 |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Usable Gates | — | 3,750 |
| Maximum Toggle Frequency | — | 40 MHz |
| 电源电压 | — | 5 V |
| Package Type | — | JLCC (windowed, ceramic, UV-erasable) |
| 引脚数量 | — | [DATA_NEEDED: pin count of LI package] |
| 安装类型 | — | Surface Mount (JLCC with J-leads) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |
| Lead Free | — | [DATA_NEEDED: lead-free] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Architecture | — | EEPROM/EPROM-based, non-volatile, instant-on |