EPM5192LC-2 vs EPM5128JC-2 对比

详细并排对比 EPM5192LC-2 出自 Altera 和 EPM5128JC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192LC-2 EPM5128JC-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $7.95 $21.75
Family MAX 5000 MAX 5000
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable Programmable Logic Device (PLD)
Macrocells 192 128
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 —
Dedicated Input Pins 7 —
External Clock Inputs 1 —
Propagation Delay (tPD) 45 ns (typical, -2 speed grade) 45 ns (max)
Maximum Internal Frequency 50 MHz —
Interconnect Programmable Interconnect Array (PIA) —
Process Technology CMOS CMOS
封装 PQCC-84 (PLCC-84, J-lead, surface mount) 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Programming Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) —
工作温度 [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range]
电源电压 5 V (typical MAX 5000 family) 5 V (nominal)
RoHS 状态 [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] Non-compliant (ceramic windowed package contains lead-bearing solder)
Dedicated Inputs — 7
Maximum Counter Frequency (fCNT) — 50 MHz
Input Setup Time (tSU) — 7.5 ns
Output Drive Current (IOH/IOL) — 12 mA DC
安装类型 — Surface Mount
Program/Erase Method — UV (ceramic window)
Erase/Program Cycles — [DATA_NEEDED: minimum erase/program cycles]
Logic Family — TTL-compatible I/O

数据手册与资源

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